Corresponding author: Ivannikov Aleksandr D., D. Sc., Deputy Director, Institute for Design Problems in Microelectronics of the Russian Academy of Sciences, Moscow, 124365, Russian Federation, e-mail: adi@ippm.ru

Accepted on September 04, 2017

Digital control systems are considered, the functioning of which can be represented as a sequence of functions from a finite alphabet. For such systems projects debugging by simulation it is necessary to generate the minimal complete, in the sense of a particular criteria, set of tests for the applying on the simulated system to verify that it is functioning correctly. Digital control sys­tems are modeled on the logic level of the signals they exchange with the external environment, including controlled object. As input data for the simulation input interactions are used, comprising both the actual input signals and output control of exchange signals. Algorithm of the minimum complete test set generation for project debugging is proposed, the algorithm is based on developer-defined classes of equivalence of input interactions. A designer chooses the set of attributes for digital system functions, the set has a hierarchical structure. Mathematically it is the definition of equivalence relation set for the set of input interactions. All input interactions causing the same digital system function fulfillment have equivalence relation. Attributes of input interaction subsets are the markers of equivalence relations. Hierarchical structure of equivalence relations is representing by bipartite graph. The full minimal test set generation is maid by processing this bipartite graph and includes all possible functions checking.
Keywords: debugging by simulation, digital system logical simulation, debugging tests